The present invention relates to a device including an electrode which has low contact resistance to a p-type Group III nitride compound semiconductor, and which does not occur any chemical reaction such as oxidation as time passes. The present invention also relates to a method for forming the electrode. As used herein, the term xe2x80x9cGroup III nitride compound semiconductorxe2x80x9d refers to a semiconductor generally represented by the following formula: AlxGayIn1-x-yN (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61, 0xe2x89xa6x+yxe2x89xa61), and examples thereof include binary semiconductors such as AlN, GaN, and InN; ternary semiconductors such as AlxGa1-xN, AlxIn1-xN, and GaxIn1-xN (in each case, 0 less than x less than 1); and quaternary semiconductors represented by the following formula: AlxGayIn1-x-yN (0 less than x less than 1, 0 less than y less than 1, 0 less than x+y less than 1). Unless otherwise specified, in the present specification, the term xe2x80x9cGroup III nitride compound semiconductorxe2x80x9d also includes p-type or n-type Group III nitride compound semiconductors doped with an impurity.
Group III nitride compound semiconductors have direct transition and whose emission spectrum can be changed over a wide range from UV to red when used in a device such as a light-emitting device. Therefore Group III nitride compound semiconductor have been used in light-emitting devices such as a light-emitting diodes (LEDs) and laser diodes (LDs). In addition, since a Group III nitride compound semiconductor has a wide band gap, a device employing the semiconductor is considered to be operated reliably at high temperature, as compared with a device employing a semiconductor other than a Group III nitride compound semiconductor. Therefore, applying group III nitride compound semiconductors to electron devices including an FET, have been developed. Moreover, because arsenic (As) is not contained in Group III nitride compound semiconductors as a main constitution element, application of the semiconductors to the various semiconductor devices has been expected from the environmental viewpoint.
In general, when a metallic layer is merely formed on the surface of a compound semiconductor, ohmic contact between the metallic layer and the compound semiconductor fails to be obtained. Therefore, conventionally, the ohmic contact can be obtained by thermal treatment of the sample to diffuse the metal in the semiconductor. In the case of a p-type Group III nitride compound semiconductor, a resistivity of the p-type Group III nitride semiconductor is not reduce to the same level of that of n-type semiconductor, even the sample is taken heat treatment process or electron beam irradiation process. Therefore, the current does not spread in a lateral direction in the p-type layer, but flows just below electrade. Accordingly light is emitted merely from a portion directly beneath the electrode. To solve this problem, there has been proposed a current-diffusing electrode which is formed by laminating a nickel (Ni) layer (thickness: some hundreds xc3x85) and a gold (Au) layer (thickness: some hundreds xc3x85) and performing heat treatment thereafter, which exhibits light transmittance and ohmic characteristics (Japanese Patent Application Laid-Open (kokai) No. 6-314822). However, this electrode of two-layer structure including a nickel (Ni) layer and a gold (Au) layer has a contact resistivity as high as 2xc3x9710xe2x88x923 xcexa9cm2 when the electrode contacts with a p-type Group III nitride compound semiconductor but the resistivity is still high. Therefore, a Group III nitride compound semiconductor device having this electrode still has a high operation voltage.
The present inventors have previously applied for a patent regarding an invention related to a p-electrode including a titanium (Ti) layer and a tantalum (Ta) layer (Japanese Patent Application No. 10-202697). This p-electrode is superior to the aforementioned electrode of two-layer structure including a nickel (Ni) layer and a gold (Au) layer in terms of initial contact resistivity, but there still remains room for improvement of the p-electrode. That is, when the p-electrode including a titanium (Ti) layer and a tantalum (Ta) layer is exposed to air for one week, the contact resistance of the electrode increases by a factor of about 1,000. The reason for the increase in contact resistance is thought to be as follows: the two-metallic-layer electrode is oxidized by oxygen and moisture contained in air; or a metal nitride is formed by nitrogen contained in a Group III nitride compound semiconductor which is in contact with the electrode. As a result, the ohmic contact can not keep low contact resistance.
The present invention has been accomplished in order to solve the aforementioned problems. An object of the present invention is to provide an electrode which has low contact resistance to a p-type Group III nitride compound semiconductor, and which does not occur any chemical reaction such as oxidation as time passes.
In order to solve the aforementioned problems, a first feature of the invention can be employed. Through use of this feature, a member selected from the group consisting a titanium nitride (TiNx) electrode, a tantalum nitride (TaNx) electrode, and a tantalum titanium nitride (TayTi1-yNz) electrode is formed on a p-type Group III nitride compound semiconductor. The titanium nitride (TiNx) electrode, tantalum nitride (TaNx) electrode, or tantalum titanium nitride (TayTi1-yNz) electrode formed on the p-type Group III nitride compound semiconductor is not oxidized by oxygen or moisture contained in air, and is not chemically reacted with nitrogen (N) atoms contained in the Group III nitride compound semiconductor which is in contact with the electrode. Therefore, the characteristics of the titanium nitride (TiNx) electrode, tantalum nitride (TaNx) electrode, and tantalum titanium nitride (TayTi1-yNz) electrode do not vary as time passes. A reduction of the contact resistance greatly contributes to suppression of generating heat in a semiconductor device, and improving the life time of the device.
A second feature of the invention includes heat treatment of a member selected from the group consisting the tantalum nitride (TaNx) electrode, titanium nitride (TiNx) electrode, and tantalum titanium nitride (TayTi1-yNz) electrode at 700 to 1,000xc2x0 C. after deposition of the electrode. Because the tantalum nitride (TaNx) electrode, titanium nitride (TiNx) electrode, or tantalum titanium nitride (TayTi1-yNz) electrode is alloyed with the Group III nitride compound semiconductor which is in contact with the electrode through this heat treatment, the value of the contact resistance can be further reduced.
A third feature of the invention is a method for forming a p-electrode of a device including a p-type Group III nitride compound semiconductor, the method comprising forming the p-electrode made of a member selected from the group consisting tantalum nitride (TaNx), titanium nitride (TiNx), and tantalum titanium nitride (TayTi1-yNz) by sputtering. Such metal nitride electrode can be formed readily by sputtering.
A fourth feature of the invention includes reactive sputtering by use of a mixing gas of nitrogen and a rare gas. By employment of a mixing gas of nitrogen and a rare gas, nitrogen atoms for forming a metal nitride can be readily generated, and thus such a metal nitride electrode can be formed more readily.
A fifth feature of the invention includes heat treatment at 700 to 1,000xc2x0 C. after sputtering. Through heat treatment, the metal nitride electrode is alloyed with the Group III nitride compound semiconductor which is in contact with the electrode, and therefore, contact resistance can be further reduced.
The present invention can be carried out with reference to the following description.
A metal nitride electrode is preferably formed of electrically conductive titanium nitride (TiN) or tantalum nitride (TaN). The electrode may be formed of zirconium nitride (ZrN), niobium nitride (NbN), or tungsten nitride (WN). Furthermore, the electrode may be formed of a mixture of these metal nitrides. The metal nitride electrode may be formed by, for example, reactive sputtering. In the case of sputtering, introduction of nitrogen (N) atoms is required. Introduction of nitrogen atoms can be realized through reaction in a gas mixture of nitrogen (N2) and an inert gas such as a rare gas (e.g., helium (He), neon (Ne), argon (Ar), or krypton (Kr)). After formation of the electrode, heat treatment is preferably carried out at 700 to 1,000xc2x0 C., more preferably at 800 to 950xc2x0 C.
When Group III nitride compound semiconductor layers are successively formed on a substrate, the substrate may be formed of an inorganic crystal compound such as sapphire, silicon (Si), silicon carbide (SiC), spinel (MgAl2O4), ZnO, or MgO; a Group III-V compound semiconductor such as gallium phosphide or gallium arsenide; or a Group III nitride compound semiconductor such as gallium nitride (GaN). The Group III nitride compound semiconductor layers are preferably formed by metal-organic chemical vapor deposition (MOCVD) or metal-organic vapor phase epitaxy (MOVPE), but may be formed by molecular beam epitaxy (MBE), halide vapor phase epitaxy (Halide VPE), or liquid phase epitaxy (LPE). The Group III nitride compound semiconductor layers may be formed by different growth methods.
For example, when layers of a Group III nitride compound semiconductor are formed on a sapphire substrate, in order to obtain a high quality simple crystal, it is preferable to form a buffer layer so as to compensate lattice mismatching with the sapphire substrate. It is also preferable to provide a buffer layer when using the different substrate. As a buffer layer, a Group III nitride compound semiconductor which is formed at a low temperature such as AlxGayIn1-x-yN (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61, 0xe2x89xa6x+yxe2x89xa61) and more preferably AlxGa1-xN (0xe2x89xa6xxe2x89xa61) is used. This buffer layer may be a single layer or multiple layers having different compositions. The buffer layer may be formed at a low temperature of 380 to 420xc2x0 C., or the buffer layer may be formed by MOCVD at a temperature in the range of 1,000 to 1,180xc2x0 C. Alternatively, a buffer layer comprising AlN can be formed by reactive sputtering using a DC magnetron sputtering apparatus and high purity metallic aluminum and nitrogen gas are used for source material. Similarly, a buffer layer expressed by the general formula AlxGayIn1-x-yN (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61, 0xe2x89xa6x+yxe2x89xa61, with the composition ratio being arbitrary) can be formed. Furthermore, it is possible to use the vapor deposition method, the ion plating method, the laser abrasion method, or the ECR method. Formation of the buffer layer by physical vapor deposition is preferably carried out at a temperature in the range of 200 to 600xc2x0 C. More preferably it is carried out at a temperature in the range of 300 to 600xc2x0 C. and still more preferably in the range of 350 to 450xc2x0 C. When a physical vapor deposition method such as these sputtering methods is used, the thickness of the buffer layer is preferably in the range of 100 to 3,000 xc3x85. More preferably it is in the range of 100 to 400 xc3x85, and most preferably it is in the range of 100 to 300 xc3x85. A multi layer may comprise, for example, alternating AlxGa1-xN (0xe2x89xa6xxe2x89xa61) layers and GaN layers. Alternatively, a multi layer may comprise alternating layers of the same composition formed at a temperature of not higher than 600xc2x0 C. and at a temperature of not lower than 1000xc2x0 C. Of course, these arrangements may be combined. Also, a multi layer may comprise three or more different types of Group III nitride compound semiconductors AlxGayIn1-x-yN (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61, 0xe2x89xa6x+yxe2x89xa61). Generally, a buffer layer is amorphous and an intermediate layer is singlecrystalline. Repetitions of unit of a buffer layer and an intermediate layer may be formed, and the number of repetitions is not particularly limited. The greater the number of repetitions, the more improvement in crystallinity.
A portion of Group III elements of a buffer layer and that of a Group III nitride compound semiconductor formed on the buffer layer may be replaced with boron (B) or thallium (Tl), or a portion of nitrogen (N) atoms of a buffer layer or that of a Group III nitride compound semiconductor formed on the buffer layer may be replaced with phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). Also, the buffer layer and the Group III nitride compound semiconductor may be doped with any elements which cannot express the composition thereof. For example, a Group III nitride compound semiconductor which is represented by AlxGa1-xN (0xe2x89xa6xxe2x89xa61) and which does not contain indium (In) and arsenic (As) may be doped with indium (In), which is larger in atomic radius than aluminum (Al) and gallium (Ga), or arsenic (As), which is larger in atomic radius than nitrogen (N), to thereby improve crystallinity by compensation, that is, the expansion strain by doped large atom compensates the compressive strain by nitrogen vacancy. In this case, since acceptor impurities easily occupy the positions of Group III atoms, p-type conductivity can be obtained as grown. Through the thus-attained improvement of crystallinity combined with the features of the present invention, dislocation density can be more reduced to approximately {fraction (1/100)} to {fraction (1/1000)}. In the case of an underlying layer comprising two or more repetitions of a buffer layer and a Group III nitride compound semiconductor layer, the Group III nitride compound semiconductor layers are further preferably doped with an element greater in atomic radius than a predominant component element. In the case where a light-emitting device is a target product, use of a binary or ternary Group III nitride compound semiconductor is preferred.
When an n-type Group III nitride compound semiconductor layer is formed, a Group IV or Group VI element, such as Si, Ge, Se, Te, or C, can be used as an n-type impurity. A Group II or Group IV element, such as Zn, Mg, Be, Ca, Sr, or Ba, can be used as a p-type impurity. The same layer may be doped with a plurality of n-type or p-type impurities or doped with both n-type and p-type impurities.
Optionally, dislocations of a Group III nitride compound semiconductor layer may be reduced through lateral epitaxial overgrowth. In order to reduce dislocations, lateral epitaxial growth. Here a mask may be performed, or trenches formed through etching may be filled through lateral epitaxial growth.
An etching mask may be formed of a single film or a multi-layer film formed from a polycrystalline semiconductor such as polycrystalline silicon or a polycrystalline nitride semiconductor; an oxide or a nitride, such as silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide (TiOx), or zirconium oxide (ZrOx); or a metal of high melting point, such as titanium (Ti) or tungsten (W). The film may be formed through any known method, such as a vapor-growth method (e.g., deposition, sputtering, or CVD).
When etching is carried out, reactive ion-beam etching (RIBE) is preferably performed, but the etching method is not limited to reactive ion-beam etching. Trenches having a V-shaped cross section (i.e., trenches having no bottom surface) may be formed through anisotropic etching, so as not to form trenches having inner walls perpendicular to a substrate.
A semiconductor device such as an FET or a light-emitting device may be formed on a Group III nitride compound semiconductor. When a light-emitting device is formed, a light-emitting layer may have a multiple quantum well (MQW) structure, a single quantum well (SQW) structure, a homo junction structure, a hetero junction structure, or a double hetero junction structure. The light-emitting layer may contain a pin junction or a pn junction.